1. Field of the Invention
The present invention relates generally to semiconductor memory devices. More particularly, the present invention relates to a storage node structure of a stack capacitor and fabrication method thereof.
2. Description of the Prior Art
It has been the trend to scale down the sizes of memory cells to increase the integration level and thus memory capacity of a DRAM chip in the semiconductor industry. As the sizes of DRAM devices are decreased, the capacity of a capacitor in the DRAM devices is correspondingly decreased. One approach to increasing capacity of the capacitor involves increasing the surface area of the storage node. As known in the art, the surface area of a storage node in a capacitor-over-bit-line (COB) structure is mostly increased by increasing the height as the design rule limits the horizontal dimension of the storage node. However, increasing the height of the storage node causes structure instability of the storage node, which is the cause of device failure due to two-bit or multi-bit failure during DRAM operation.
FIGS. 1-5 are schematic, cross-sectional diagrams showing a conventional method for fabricating a storage node of a crown-type stacked cell capacitor. As shown in FIG. 1, a substrate 10 such as a silicon substrate having thereon conductive blocks 12a and 12b is provided. A dielectric layer 14 such as silicon nitride and a dielectric layer 16 such as undoped silicate glass (USG) are deposited over the substrate 10.
As shown in FIG. 2, a conventional lithographic process and a dry etching process are carried out to define high aspect ratio openings 18a and 18b in the dielectric layers 14 and 16. Subsequently, a cleaning process may be performed to remove the etching byproducts or particles from the surfaces of the substrate 10 and from the interior surfaces of the openings 18a and 18b. 
As shown in FIG. 3, a chemical vapor deposition (CVD) process is carried out to form a conformal silicon layer 22 on the surface of the dielectric layer 16 and on the interior surfaces of the openings 18a and 18b. The silicon layer 22 may be doped polysilicon.
As shown in FIG. 4, a planarization process such as chemical mechanical polishing (CMP) is performed to selectively remove the silicon layer 22 from the surface of the dielectric layer 16, while leaving the silicon layer 22 on the interior surfaces of the openings 18a and 18b intact.
Subsequently, as shown in FIG. 5, a wet etching process involving the use of HF/NH4F chemistry or Buffer Oxide Etcher (BOE) is performed to remove the dielectric layer 16, thereby forming storage nodes 30a and 30b. Typically, the height H of each of the storage nodes 30a and 30b is approximately equal to the depth of the openings 18a and 18b, which is normally 1.6-1.7 micrometers.
One drawback of the above-mentioned prior art method is that when forming the high aspect ratio openings 18a and 18b it is difficult to obtain a straight sidewall profile. The tapered sidewall profile of the high aspect ratio openings 18a and 18b leads to small bottom critical dimension A. The small bottom critical dimension A results in so-called storage node bridge phenomenon during subsequent cleaning or drying processes.